A conventional CMOS OR circuit (e.g. the 3-input OR circuit 10 of FIG. 1) is slow, inhibiting its use in the critical speed path of an Integrated Circuit (IC).
FIG. 2 shows a known 3-input OR circuit 20, which is undesirably slow when designed to be operable under all temperatures, process corners and supply voltages. Furthermore, the speed of OR circuit 20 varies significantly with temperature, process and supply voltage variations.
FIG. 3 shows a computer simulation of a timing delay between input terminal IN1 and output terminal OUT of OR circuit 20, under a nominal operation condition, (i.e. typical process corner, 25.degree. C. and 5 volts supply voltage). Using the midpoint between the positive and the negative supply voltages (i.e. 2.5 volts) to measure the delay, it is seen from FIG. 3 that a delay of 0.36 nsec exists between the time the input signal IN1 crosses the 2.5 volts and the time when output signal OUT crosses the same voltage level. The 0.36 nsec delay is undesirably high for some applications.
Therefore a need exists for a CMOS OR circuit which is relatively insensitive to changes in temperature, process and supply voltage variations and operates at a high speed under a nominal operating condition.